1. Technical Field
The present invention relates to an apparatus for data processing in general, and in particular to a binary adder. Still more particularly, the present invention relates to a high-speed carry-lookahead binary adder.
2. Description of the Prior Art
Binary adders having a carry-lookahead are well known in the art. This type of binary adder is able to add two multiple-bit binary numbers while simultaneously computing a carry signal for each bit.
In order to compute the sum of two multiple-bit binary numbers A and B, a generate signal and a propagate signal are initially produced at each bit location. The equation for a generate signal G(i) is G(i)=A(i)B(i), and the equation for propagate signal P(i) is P(i)=A(i)B(i)+A(i)B(i) or A(i){character pullout}B(i), where i denotes a bit location within the binary umbers having bit 0 as the most significant bit. These generate signals and propagate signals are then utilized to produce a carry signal for each bit. The generalized equation for a carry signal C(i) is C(i)=G(i)+P(i)G(i+1)+P(i)P(i+1)G(i+2)+P(i)P(i+1)P(i+2)G(i+3)+ . . . , etc.
The present disclosure provides an improved binary adder capable of producing group generate signals and group propagate signals with fewer levels of logic than is required by the prior art.